http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H05109911-A

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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205
filingDate 1991-10-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5029b2bec37564a2c9597b76dbd57007
publicationDate 1993-04-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H05109911-A
titleOfInvention Semiconductor device and manufacturing method thereof
abstract (57) [Summary] [Object] In a semiconductor device in which an interlayer insulating film is flattened by SOG, a V-shaped groove generated when a silicon oxide film is formed is removed to eliminate a void generated when SOG is applied. Improves moisture resistance and reliability. [Structure] After forming a wiring layer 14 of polysilicon or the like, A silicon oxide film 15 formed by a plasma CVD method using organic silicon as a main material is formed, isotropically etched back, and then SOG 16 having a low shrinkage ratio is applied and cured. Further, in some cases, a silicon oxide film 17 is formed by the CVD method to serve as an interlayer insulating film.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-5698467-A
priorityDate 1991-10-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 20.