http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H05109720-A

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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205
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filingDate 1991-10-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_157dd474948368e8a2673057426850d3
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fcbba40cc217f56923eee11488872c7f
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publicationDate 1993-04-30-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H05109720-A
titleOfInvention Method for manufacturing semiconductor device
abstract (57) [Abstract] [Objective] After the first insulating film containing impurities is formed on the entire surface of the substrate, the second insulating film is formed by a reaction having strong surface reactivity. The surface reaction is stabilized and the surface of the substrate is flattened by the second insulating film. [Structure] S on which a circuit element and a first Al wiring 4 are formed The BPSG film 6 is deposited on the i substrate 1, and then the atmospheric pressure CV is applied. A SiO 2 film 8 containing no impurities is deposited by the thermal decomposition reaction of TEOS and oxygen containing ozone by the D method. At this time, In the step portion of the Al wiring 4, the SiO 2 film 8 has a gentle slope and a flattened shape can be obtained. Since the BPSG film 6 is formed on the entire surface of the substrate before the O 2 film 8 is deposited, the Si having a flattened shape is formed. The O 2 film 8 is stably obtained with good uniformity. Next, SiO 2 A step of etching a desired region of the film 8 and the BPSG film 6 to form a through hole, and Al as a second wiring. By performing the step of forming the wiring 10, a two-layer Al wiring is obtained.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H02163586-A
priorityDate 1991-10-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 30.