http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H03160545-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e757fd4fedc4fe825bb81b1b466a0947 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-32 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-16 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F13-00 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-362 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-32 |
| filingDate | 1990-10-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_340ab70365050f6961959b08657eca19 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a9413c63b7264bfa53c1d63e1b5be643 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_72b0e0f0c97595b7688f3d51451b873d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0e8159388e42529f5afdddabb937831f http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_74b256da7de24d9c45d0771d67535768 |
| publicationDate | 1991-07-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-H03160545-A |
| titleOfInvention | Interface circuit |
| abstract | PURPOSE: To perform the transparent forced elimination of direct memory access or other data transfer operations by providing a break-in circuit for interrupting control signals from a bus interface controller in response to data transfer request signals. n CONSTITUTION: This circuit is provided with a direct memory access controller DMAC 202, a direct memory access port DMAP controller 204 and a system bus selection slave SBSS controller 206. Then, when the operation of the DMAC 202 is actually executed in a local bus and one of the operation of the DMAP 204, the operation of the SBSS 206 and the operation of the system bus memory slave is requested, the operations break in the operation of the DMAC 202 performed at present and the operation of the DMAC 202 is tentatively interrupted. it is achieved by break-in logic 210. Thus, the data transfer of the direct memory access or the like is efficiently interrupted and restarted. n COPYRIGHT: (C)1991,JPO |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2005078161-A |
| priorityDate | 1989-11-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 23.