http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H0290382-A

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_80787665b837ed3eb503bbcd27c0043a
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F13-42
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-78
filingDate 1988-09-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ef16d762e6b66f3833c7f06d594fca45
publicationDate 1990-03-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H0290382-A
titleOfInvention Semiconductor integrated circuit
abstract PURPOSE: To improve an operation efficiency as a whole by operating asynchronously plural function modules whose maximum operation frequencies are different, and also, executing a synchronized control for a data transfer between the function modules. n CONSTITUTION: A single chip microcomputer 1 incorporates a CPU module 2, a RAM module 3, a timer counter module 4, a serial input/output circuit module 5, a DMAC module 6 and a DMAC module 7. In this state, to the modules 2, 3, 4, 6 and 7, different operation clock signals ϕ 0 , ϕ 3 , ϕ i , ϕ 1 and ϕ 2 are supplied through a frequency dividing circuit 11 from the output of a clock pulse generator 10 to which an external clock signal CLK1 and the modules execute an asynchronous operation. To the input/output circuit module 5, an independent clock signal CLK2 is applied and a data transfer which passes through a silicon pack plane bus 8 being an asynchronous bus is brought to synchronized control. In such a manner, the operation efficiency as a whole can be improved. n COPYRIGHT: (C)1990,JPO&Japio
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priorityDate 1988-09-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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