http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-H01308050-A

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classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76877
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522
filingDate 1988-05-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f890256da39da1fdbf9bf70d284da9aa
publicationDate 1989-12-12-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-H01308050-A
titleOfInvention Method for forming low-resistance contact with aluminum substance, low-resistance contact by this method, and multilayer structure for integrated circuit
abstract PURPOSE: To utilize an obtained structure for forming a multilayer conductive pattern for VLSI circuit by selectively depositing tungsten in a via hole within an insulator that is laminated on aluminum on a substrate at a wafer temperature within a specific range. n CONSTITUTION: A test structure pattern used for a first metal level in a CMOS process is executed. In the process, a wafer is oxidized, aluminum layer containing aluminum or silicon is laminated by sputtering, and bimetal level is formed on the layer. Then, silicon oxide layer is deposited by the plasma enhance PECVD and a via hole to a lower-layer metal is formed by projection lithography and reactive ion etching. Then, tungsten is selectively deposited onto a metal by hydrogen reduction of tungsten hexafluoride into it at approximately 350°C or higher and approximately 450°C or lower for preventing a hillock from being formed on an aluminum structure. Thus, a tungsten plug with a low-resistance contact can be provided in a via hole, thus manufacturing an ultra-large-scale integrated circuit device. n COPYRIGHT: (C)1989,JPO
priorityDate 1987-06-01-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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