http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-6620260-B1
Outgoing Links
| Predicate | Object |
|---|---|
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-36 |
| filingDate | 2019-07-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2019-12-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2019-12-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-6620260-B1 |
| titleOfInvention | Semiconductor device and electronic equipment |
| abstract | By applying an AC pulse to the gate of a transistor that is likely to deteriorate, a shift in threshold voltage of the transistor is suppressed. However, when amorphous silicon is used as the semiconductor layer of the transistor, it is a problem that the transistor constituting the circuit that generates the AC pulse also causes a threshold voltage shift. By inputting a signal to a gate electrode of a transistor that is easily deteriorated through a turned-on transistor, a threshold voltage shift of the transistor that is easily deteriorated and a threshold voltage shift of the turned-on transistor are suppressed. To do. That is, a configuration is included in which an AC pulse is applied to the gate electrode of a transistor that is likely to deteriorate through a transistor to which a high potential (VDD) is applied to the gate electrode (or through an element having a resistance component). [Selection] Figure 3 |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111833744-A |
| priorityDate | 2019-07-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 73.