http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-3447690-B2

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filingDate 2000-12-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2003-09-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 2003-09-16-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-3447690-B2
titleOfInvention Semiconductor chip stacking method
abstract A plurality of semiconductor chips each having an electrode surface are sequentially laminated and mounted. Initially, the electrode surfaces of the semiconductor chips are activated. Then, the semiconductor chips are positioned. Successively, the semiconductor chips are laminated and bonded by pressing such that a reaction layer is not formed or formation of the reaction layer is suppressed excessively. Finally, the semiconductor chips are entirely heated so as to form the reaction layer after lamination and bonding of all the semiconductor chips are completed.
priorityDate 2000-12-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 31.