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filingDate 2021-09-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_017ee6d1131a540278c1cedac9e70109
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publicationDate 2022-06-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2022092570-A
titleOfInvention Pillar selection transistor for 3D crosspoint memory
abstract PROBLEM TO BE SOLVED: To provide a pillar selection transistor for increasing a memory density while minimizing a footprint of a decoder transistor in a crosspoint memory array. A memory device structure 100 includes a vertical pillar selection transistor 102 having a channel layer 104 between a source structure 106 and a drain structure 108, and a gate electrode 110 adjacent to the channel. The gate dielectric layer 111 is between the gate electrode and the channel layer. The first terminal 112 of the first interconnect 112 is coupled to a source or drain structure. The memory device structure further includes a pair of memory cells 118, 120 (136, 138). Each memory cell includes a selector and a memory element. The individual first terminals of the memory cell are coupled to the second and third terminals of the first interconnect, respectively. The individual second terminals of the memory cell are individually coupled to a pair of second interconnects. [Selection diagram] FIG. 1A
priorityDate 2020-12-10-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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