http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2021141332-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fdf3b6ced3d7710ec0bc0addb67a1cc9 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0629 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1225 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-045 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-146 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 |
| filingDate | 2021-04-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_949501fab1aab8582f126f6a2d4786ac http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b1b87833dee400d096306837d47542af http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_52486da489c45dcbbd7f6a8a0f28c46a |
| publicationDate | 2021-09-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2021141332-A |
| titleOfInvention | Semiconductor device |
| abstract | PROBLEM TO BE SOLVED: To provide a semiconductor device having stable electrical characteristics. A transistor having a first to third oxide semiconductor layer, a gate electrode, and a gate insulating layer, wherein the second oxide semiconductor layer has a first oxide semiconductor layer and a third oxide. It has a portion provided between the material semiconductor layer, the gate insulating layer has a region in contact with the upper surface of the third oxide semiconductor layer, and the gate electrode and the upper surface of the above-mentioned portion are the gate insulating layer. The gate electrode and the side surface of the above-mentioned portion in the channel width direction have a region facing each other via a gate insulating layer, and the second oxide semiconductor layer has a region overlapping with each other. Thickness is 2 nm or more and 8 nm The second oxide semiconductor layer has a region of less than 60 nm and has a length of less than 60 nm in the channel width direction. [Selection diagram] Fig. 1 |
| priorityDate | 2014-07-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 71.