| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fdf3b6ced3d7710ec0bc0addb67a1cc9 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0214
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02164
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-19043
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-19041
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2221-6835
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-30105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-12044
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-14 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-568
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3114
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-295
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-293
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1203
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-562
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-6835
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-561 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 |
| filingDate |
2021-02-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8a1f180875588a75a3f18a59ddbfd094 |
| publicationDate |
2021-05-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2021082835-A |
| titleOfInvention |
Semiconductor device |
| abstract |
PROBLEM TO BE SOLVED: To reduce defects of a semiconductor device such as shape defects and characteristic defects due to breakage such as cracks due to external stress. Therefore, one of the purposes is to provide a highly reliable semiconductor device. Another object of the present invention is to improve the manufacturing yield of the semiconductor device by reducing the above-mentioned defects even during the manufacturing process. SOLUTION: In a semiconductor integrated circuit sandwiched between a pair of first impact resistant layers and a second impact resistant layer, a shock diffusion layer is provided between the semiconductor integrated circuit and the second impact resistant layer. By providing an impact resistant layer against external stress and an impact diffusing layer that diffuses the impact, the force applied per unit area of the semiconductor integrated circuit is reduced, and the semiconductor integrated circuit is protected. The impact diffusion layer preferably has a low elastic modulus and a high fracture coefficient. [Selection diagram] Fig. 1 |
| priorityDate |
2008-04-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |