| abstract |
One embodiment relates to a porous polyurethane polishing pad used in a chemical mechanical planarization (CMP) process of a semiconductor and a method for manufacturing the same, wherein the porous polyurethane polishing pad has a size of a void and a size of a porous polyurethane polishing pad. By adjusting the distribution, the polishing performance (polishing rate) of the polishing pad can be adjusted. [Selection diagram] FIG. |