http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2020188252-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_1a34d7d2e0d09a58cb7bf4a04c81162e |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53238 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76831 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76873 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76844 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205 |
| filingDate | 2020-03-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a89fc38ab938c5ed618c91a4e848cb3d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a5f0c2b36c075caeeddd88dc8d484275 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_95abb58c9e256fa169e7cd44153a4c90 |
| publicationDate | 2020-11-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2020188252-A |
| titleOfInvention | Manufacture of penetrating silicon vias |
| abstract | PROBLEM TO BE SOLVED: To form a penetrating silicon via in a silicon wafer which establishes an electrical connection via a low resistance and high density silicon wafer and at the same time maintains processability for further manufacturing. A method of depositing an upper mask on a silicon wafer 101, wherein the upper mask 102 includes a first silicon dioxide layer, a lower mask 103 is vapor-deposited on a lower portion of the silicon wafer, and through silicon. Optically patterning the via pattern 104 and etching the penetrating silicon via 105 to the upper mask, etching the penetrating silicon via using the penetrating silicon via pattern to the lower mask via the silicon wafer, and etching the silicon wafer. To remove the upper and lower masks from the silicon wafer, to grow a second hot silicon dioxide layer on the upper part of the silicon wafer, the lower part of the silicon wafer and through the silicon vias, and to grow the second hot silicon dioxide layer from the silicon wafer. Etching and including. [Selection diagram] FIG. 1C |
| priorityDate | 2019-05-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 34.