http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2020098660-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fdf3b6ced3d7710ec0bc0addb67a1cc9 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-3233 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G09G3-36 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C19-28 |
| filingDate | 2020-02-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_54968803d5f05358c2b985c27b8ca076 |
| publicationDate | 2020-06-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2020098660-A |
| titleOfInvention | Output circuit |
| abstract | PROBLEM TO BE SOLVED: To suppress stress on a transistor while suppressing occurrence of malfunction. In a pulse output circuit having a function of outputting a pulse signal and having a transistor for controlling whether or not the pulse signal is set to a high level, a pulse signal output by the pulse output circuit is at a low level. During a certain period, the potential of one of the source and the drain of the transistor is set higher than the low-level potential of the clock signal and higher than the high-level potential. Thereby, the stress on the transistor is suppressed. [Selection diagram] Figure 1 |
| priorityDate | 2012-07-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 70.