http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2020047320-A

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filingDate 2018-09-14-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2020-03-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2020047320-A
titleOfInvention Memory system and semiconductor storage device
abstract A storage capacity is suppressed from being reduced. According to one embodiment, a memory system includes a semiconductor storage device and a controller. The semiconductor memory device 100 includes a plurality of first wiring layers 31, a plurality of second wiring layers 31, a semiconductor pillar 48, a first charge storage layer 46, a second charge storage layer 46, and a plurality of first wirings. A first mode control for independently selecting one of the layers 31 and a corresponding one of the plurality of second wiring layers 31; and controlling one of the plurality of first wiring layers 31 and the plurality of second wiring layers 31 And a control unit 15 capable of performing a control in a second mode for collectively selecting the corresponding one. The controller 200 controls the control unit 15 of the semiconductor storage device 100 to control the first mode or the second mode. [Selection diagram] FIG.
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