| abstract |
A semiconductor device capable of performing normal operation of a nonvolatile memory and saving power by a P-state function, and a driving method thereof are provided. A first circuit that controls a state including a drive voltage and a clock frequency of a processor core, a first storage circuit and a second storage circuit that store state information, A second circuit for generating a power supply and a third circuit for generating a clock, the second circuit being electrically connected to the third circuit. And a processor core electrically connected to the second circuit and the third circuit via a switch, and the processor core exchanges volatile memory and data with the volatile memory. The configuration includes a nonvolatile memory. [Selection diagram] Fig. 1 |