http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2019512833-A
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-221 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1042 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-2273 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-2293 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-2257 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-12 |
| filingDate | 2017-03-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2019-05-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2019512833-A |
| titleOfInvention | Parallel access technology in multiple memory sections by section independence |
| abstract | A memory device having multiple sections of memory cells, such as ferroelectric memory cells (Hybrid RAM (HRAM) cells), may provide concurrent access to the memory cells within separate sections of the memory device. The first memory cell may be activated and the second memory cell may be determined to be independent of the first memory cell. If the second memory cell is independent of the first memory cell, the second memory cell may be activated before the operation on the first memory cell is completed. The latch hardware in the memory section can latch the address in the memory section so that the new address can be given to another section to access the second memory cell. 【Selection chart】 None |
| priorityDate | 2016-03-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 20.