http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2019204968-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fdf3b6ced3d7710ec0bc0addb67a1cc9 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-24 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-01 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-033 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-05 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-036 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 |
| filingDate | 2019-07-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dc02790645254d1c123f11c34a731412 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_949501fab1aab8582f126f6a2d4786ac |
| publicationDate | 2019-11-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2019204968-A |
| titleOfInvention | Semiconductor device |
| abstract | A high-speed operation and low power consumption, a memory capacity per unit area, and a semiconductor memory device with an increased capacity of the capacitor are provided. A semiconductor memory device 300 includes two or more sub memory cells SCL_1 to c each including a word line WL, a bit line BL, first capacitors Cf_1 to c, second capacitors Cb_1 to c, and transistors Tr_1 to c. It has the memory cell CL which has. In the memory cell, sub memory cells are formed by being stacked. The transistor is provided with a first gate and a second gate through a semiconductor film, the first gate and the second gate are connected to a word line, and one of the source and the drain of the transistor is connected to a bit line The other of the source and the drain of the transistor is connected to the first capacitor and the second capacitor, and the first gate and the second gate of the transistor in each of the sub memory cells are overlapped and connected. [Selection] Figure 1 |
| priorityDate | 2011-12-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 75.