http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2019149220-A

Outgoing Links

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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04
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filingDate 2018-10-10-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f472f8a1c87d107c73ba732f16570d0c
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publicationDate 2019-09-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2019149220-A
titleOfInvention Semiconductor memory device and memory system
abstract [PROBLEMS] To improve reliability. According to an embodiment, a semiconductor memory device includes a first memory unit SU0 including first to third memory cells MT, a second memory unit SU1 including fourth to sixth memory cells MT, and a first memory unit SU1. A third memory unit SU2 including the seventh to ninth memory cells MT is included. When performing the second write operation on any of the first, fourth, and seventh memory cells connected to the first word line, the first memory cell is first selected and connected to the second word line When performing the second write operation on any of the second, fifth, and eighth memory cells, the fifth memory cell is first selected and connected to the third word line. When performing the second write operation on any of the nine memory cells, the ninth memory cell is selected first. [Selection] FIG.
priorityDate 2018-02-27-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

Incoming Links

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Total number of triples: 17.