http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2019129179-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_47cc435e1d443f13180f7766df104d9d |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-12 |
| filingDate | 2018-01-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d9a43def53609aa519438791dc05e3e1 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f62a820edc6182247d5a473962bd79a4 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0d4b9c3b271f4020e339aac2ffce71a9 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_34b34635c99769d594d8c55ae378286a http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ecebcf050662cb3cdd40287af8a963df |
| publicationDate | 2019-08-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2019129179-A |
| titleOfInvention | Manufacturing method of semiconductor device |
| abstract | A semiconductor device manufacturing method capable of simplifying a semiconductor device manufacturing process in which warpage is suppressed is provided. A temporary fixing material preparation step (a) of preparing a temporary fixing material comprising a base material and a warpage suppressing layer in a semi-hardened state, the back surface of the bump surface of a plurality of singulated semiconductor elements is A mounting step (b) for mounting on the warpage suppressing layer of the temporarily fixing material, a sealing step (c) for sealing the semiconductor element with a sealing material, and a substrate removing step for removing the substrate of the temporarily fixing material ( d), a polishing step (e) for polishing the sealing material until the bumps of the semiconductor element are exposed, and a rewiring formation step (f) for forming a rewiring layer on the bump surface of the semiconductor element, A method for manufacturing a semiconductor device, wherein the thickness of the warp suppressing layer is 0.4 to 2.5 times the thickness from the bump surface to the surface of the sealing material of the semiconductor element. [Selected figure] Figure 2 |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-WO2022118929-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-7226664-B2 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2022185489-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2022186372-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2022118929-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2022118480-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2022118479-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-7243934-B2 |
| priorityDate | 2018-01-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 73.