| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f8e7780b6442925fa39eee8382aa6c9f |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02M3-075
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02M3-076
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0629 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L28-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5223
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0629
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H02M3-073
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-145
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-30 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H02M3-07
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3205
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H02M3-155
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04 |
| filingDate |
2017-11-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_244532b1f232e8a4239f78ca43e0277d |
| publicationDate |
2019-06-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2019096821-A |
| titleOfInvention |
Semiconductor device |
| abstract |
To provide a semiconductor device capable of reducing a layout area. A semiconductor substrate 20, at least one circuit block formed on a main surface 31 of the semiconductor substrate 20 and having a predetermined function, and a plurality of metal layers M1 to M4 connecting the circuit blocks are provided. Wiring, a first capacitance CM connected to the circuit block and using the metal layers M1 to M4, and a second capacitance CC using the active region 21 formed in the main surface 31 of the semiconductor substrate 20. And a plurality of mixed capacitors, and at least one of the first capacitors CM and at least one of the second capacitors CC are stacked in the stacking direction of the semiconductor layers. [Selected figure] Figure 5 |
| priorityDate |
2017-11-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |