| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0f705f295f4ba571f5311e5ef1b57807 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2203-0723
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2201-09827
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-4661
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2203-107 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-4644
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-0038
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K1-115
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-429
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-465
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-424 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-46 |
| filingDate |
2017-10-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d72e9fbb19ba2bbf31d0e1c7856da0b6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e386e721935f721034dbfb7fa4df091d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_66e83285b1d570da31de46e85ef82c26 |
| publicationDate |
2019-05-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2019079899-A |
| titleOfInvention |
Printed wiring board |
| abstract |
PROBLEM TO BE SOLVED: To provide a printed wiring board having high reliability. A printed wiring board 10 according to an embodiment has a core substrate 30 having a first surface F and a second surface S and a first build on the first surface F. It is formed by the second buildup layer Bu2 on the upper layer Bu1 and the second surface S. The core substrate 30 has the core layer 20 and the conductor layers 34F and 34S on the core layer, and the first and second buildup layers Bu1 and Bu2 are the outermost conductor layers with the inner conductor layers 58F, 158F, 58S and 158S. It has 258F and 258S. The thickness of at least one inner conductor layer in the buildup layers Bu1 and Bu2 is smaller than the thickness of the outermost conductor layer and the thickness of the conductor layer of the core substrate. [Selected figure] Figure 2 |
| priorityDate |
2017-10-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |