| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fdf3b6ced3d7710ec0bc0addb67a1cc9 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-1156
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 |
| filingDate |
2017-09-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e8f6c32820559267d29f37135e1ed272
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f922de40c506774db116bcd492a03bae
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a88c4abe293be1cc62560cf6492fb221
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_087372e577a4b98d7e7a895f5a1d1071 |
| publicationDate |
2019-03-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2019047046-A |
| titleOfInvention |
Integrated circuits, computers and electronics |
| abstract |
PROBLEM TO BE SOLVED: To provide a novel integrated circuit. An integrated circuit having a plurality of arithmetic circuits corresponding to a hidden layer and an output layer of a neural network. The arithmetic circuit has a product-sum arithmetic circuit and a hierarchical output circuit. The arithmetic circuit has a function of outputting third data corresponding to the result of the product-sum operation of the first data and the second data, and the hierarchical output circuit uses the third data as an activation function. It has a function of converting based on it and outputting analog data or multi-value digital data. The data is input to the product-sum operation circuit of the next operation circuit without being converted into binary digital data. By unifying the channel length direction of the transistor of the memory cell among the plurality of product-sum operation circuits, it is possible to reduce the variation in the transistor characteristics of the memory cell. [Selected figure] Figure 3 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2023139990-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2022229789-A1 |
| priorityDate |
2017-09-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |