http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2018537852-A

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filingDate 2016-10-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 2018-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2018537852-A
titleOfInvention Power rail inbound middle-of-line (MOL) routing
abstract In certain aspects, the semiconductor die includes a power rail, a first gate, and a second gate. The semiconductor die also has a first gate contact electrically coupled to the first gate, wherein the first gate contact is formed from a first middle-of-line (MOL) metal layer; A second gate contact electrically coupled to the second gate, wherein the second gate contact is formed from a first MOL metal layer. The semiconductor die further includes an interconnect formed from the second MOL metal layer, wherein the interconnect is electrically coupled to the first and second gate contacts, wherein at least a portion of the interconnect includes a power Located at the bottom of the rail. [Selection] Figure 9
priorityDate 2015-11-09-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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isDiscussedBy http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419578708

Total number of triples: 27.