| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e5db580deca7130dbe51805c6c608b35 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06541
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06527
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06517
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06513
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06565
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-1058
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5286 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-15026
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49816
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-0657 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-07
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-065
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-822
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-82 |
| filingDate |
2017-04-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bbd070b3357075890efef43391a66d40 |
| publicationDate |
2018-11-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2018182213-A |
| titleOfInvention |
Semiconductor device and method of manufacturing semiconductor device |
| abstract |
An object of the present invention is to realize a high-performance semiconductor device capable of high density three-dimensional mounting by improving the degree of wiring congestion. A semiconductor device includes a first semiconductor die 1 and a second semiconductor die 2 connected on the first semiconductor die 1. The first semiconductor die 1 has two stages of a clock tree structure 4. The second semiconductor die 2 has the logic circuit 5 electrically connected to the buffer 4 b of the N-th stage configuration. The second semiconductor die 2 has the buffer 4 b of the N-th stage configuration (N is an integer of 3 or more). doing. [Selected figure] Figure 5 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2023127385-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2023112682-A1 |
| priorityDate |
2017-04-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |