http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2018124977-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fdf3b6ced3d7710ec0bc0addb67a1cc9 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2207-4814 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-5443 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06N3-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06N3-065 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-363 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06G7-60 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06N3-063 |
| filingDate | 2017-10-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_087372e577a4b98d7e7a895f5a1d1071 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e8f6c32820559267d29f37135e1ed272 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a88c4abe293be1cc62560cf6492fb221 |
| publicationDate | 2018-08-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2018124977-A |
| titleOfInvention | Semiconductor device and system having the semiconductor device |
| abstract | A semiconductor device capable of product-sum operation is provided. A semiconductor device having a first memory cell, a second memory cell, and an offset circuit, wherein the first memory cell holds first analog data and the second memory cell holds reference analog data. Then, by applying a potential corresponding to the second analog data as a selection signal, a current depending on the product sum of the first analog data and the second analog data is acquired. The offset circuit includes a constant current circuit, and the constant current circuit includes a transistor and a capacitor. The first terminal of the transistor is electrically connected to the first gate of the transistor and the first terminal of the capacitor, and the second gate of the transistor is electrically connected to the second terminal of the capacitor. Yes. By holding the potential between the first terminal and the second gate of the transistor with a capacitor, fluctuation in current flowing between the source and drain of the transistor is suppressed. [Selection] Figure 3 |
| priorityDate | 2016-10-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 43.