http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2018110141-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f56b5174f7d196258707ccf1d609796e |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-32135 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-35 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-40117 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42344 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-792 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66833 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate | 2016-12-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2ed41c8adc940bdbb4c2844b192fc68a http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_34c906437c735ab71700c14c5875f994 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a2b6e82cae6b9614776992c1a32100cb |
| publicationDate | 2018-07-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2018110141-A |
| titleOfInvention | Semiconductor device and manufacturing method thereof |
| abstract | In a split gate type MONOS memory, an increase in a defect rate due to a variation in gate length of a memory gate electrode is prevented, and reliability of a semiconductor device is improved. A silicon film is subjected to first dry etching having strong anisotropy and low selectivity to silicon oxide, and then performing second dry etching having low anisotropy and high selectivity to silicon oxide. Thus, after forming the control gate electrode CG made of the silicon film, the sidewall-shaped memory gate electrode MG is formed on the side surface of the control gate electrode CG. Here, in the first dry etching, the length of the etching time is determined in accordance with the desired characteristics of the memory to be manufactured and the film thickness of the silicon film in accordance with the etching time setting table, so that the first dry etching and the second dry etching are performed. The amount of each dry etching is controlled, thereby controlling the gate length L1 of the memory gate electrode MG. [Selection] Figure 6 |
| priorityDate | 2016-12-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 36.