http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2017532686-A
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D30-50 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D10-00 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-3287 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-3275 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-324 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-3243 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-3296 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-32 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-177 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-26 |
| filingDate | 2015-10-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2017-11-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2017532686-A |
| titleOfInvention | New low cost, low power high performance SMP / ASMP multiprocessor system |
| abstract | The processing system includes a multiprocessor in which the first processor operates at a first clock frequency and a first supply voltage at all times. The at least one processor may be at a first clock frequency and a first supply voltage, or the first processor and the second processor, where the first processor and the second processor provide symmetric multiprocessing (SMP) provision. Is dynamically switchable to operate at a second clock frequency and a second supply voltage resulting in provision of asymmetric multiprocessing (ASMP). A third processor that further operates at the first clock frequency and the first supply voltage at all times may be included. Various criteria can be used to determine when to switch at least one switchable processor to improve power consumption and / or performance. The controller enables control and fast switching between the two modes of the switchable processor. Upon receipt of a switch command that switches between SMP and ASMP, a continuous or series of actions are performed to control the voltage supply and CPU / memory clock to the switchable processor and cache memory. |
| priorityDate | 2014-10-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 67.