http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2017182854-A

Outgoing Links

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c3a2f00e72ba6e4c09b6da573427fbed
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-846
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-406
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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-406
filingDate 2016-03-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b85dea049c8944a0b6bc07f3f5109ab8
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publicationDate 2017-10-05-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2017182854-A
titleOfInvention Semiconductor device
abstract A circuit for analyzing a history of access to a memory cell is reduced. A semiconductor device according to an aspect of the present invention provides access to a plurality of volatile memory cells MC, a plurality of word lines WL respectively connected to the plurality of volatile memory cells MC, and the plurality of word lines WL. Intermittent monitoring, captured row addresses are sequentially stored / erased in a predetermined number of registers, and a predetermined number of accesses to the same word line WL within a predetermined period A control circuit 40A for detection is provided by comparison. According to the present invention, an access history can be accurately analyzed with a small circuit configuration, and for example, a Row Hammer problem can be dealt with. [Selection] Figure 1A
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11417385-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I655627-B
priorityDate 2016-03-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 21.