| abstract |
A semiconductor memory device with high speed operation and low power consumption, and a semiconductor memory device in which a memory capacity per unit area is increased and a capacity of a capacitor is increased. A semiconductor memory device includes a memory cell having two or more sub memory cells each including a word line, a bit line, a first capacitor, a second capacitor, and a transistor. In a memory cell, sub memory cells are stacked, and the transistor is provided with a first gate and a second gate through a semiconductor film, and the first gate and the second gate are connected to a word line. One of the source and the drain of the transistor is connected to the bit line, the other of the source and the drain of the transistor is connected to the first capacitor and the second capacitor, and the first gate and the second gate of the transistor in each of the sub memory cells. Two gates overlap and connect. [Selection] Figure 1 |