http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2017092327-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0f705f295f4ba571f5311e5ef1b57807 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48227 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-83385 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16225 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-32225 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-73204 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-34 |
| filingDate | 2015-11-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3c6aebccda7fe365ba4d1bff22b357ae http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4262c8aa426b31975b9fe74285601290 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_570b2ad9456cfbbefdb435697eda65b2 |
| publicationDate | 2017-05-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2017092327-A |
| titleOfInvention | Printed wiring board, printed wiring board manufacturing method, and semiconductor device |
| abstract | An object of the present invention is to prevent migration from occurring while preventing outflow of an underfill filled between a semiconductor element and a printed wiring board. A printed wiring board includes a base insulating layer made of an insulating material and a plurality of pads formed on at least one of a first surface and a second surface of the base insulating layer. 14a and a conductor layer 14 including wirings 14b, and a solder resist layer 16 having a plurality of openings 17 corresponding to the pads 14a. The solder resist layer 16 includes a first solder resist layer 18 formed on at least one surface of the base insulating layer 12 and the wiring 14b, and a second solder resist layer 19 formed on the first solder resist 18. And a groove 21 that at least partially surrounds the plurality of pads 14a. The groove bottom 21 b of the groove 21 is configured by the outer surface of the first solder resist layer 18. [Selection] Figure 1 |
| priorityDate | 2015-11-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 23.