| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9ec030fc062b270c25327af9127bed3a |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-15311
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-1058
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49838
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-73204
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-32225 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-49822
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-53228
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-4846 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-46
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-38
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-34 |
| filingDate |
2015-10-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8723fd9d93e8b211e7344c56254b1b09 |
| publicationDate |
2017-04-06-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2017069524-A |
| titleOfInvention |
Wiring board and manufacturing method thereof |
| abstract |
A wiring board capable of securing a wiring layer having a desired thickness is provided. The wiring board includes a semiconductor chip mounting surface and an external connection surface opposite to the semiconductor chip mounting surface, the outermost wiring layer on the semiconductor chip mounting surface side. A first wiring layer, a second wiring layer serving as the outermost wiring layer on the external connection surface side, and one or more insulating layers formed between the first wiring layer and the second wiring layer And the first wiring layer includes a semiconductor chip mounting pad and a first wiring pattern extending from the semiconductor chip mounting pad, the semiconductor layer mounting surface side of the insulating layer The roughness of the first exposed surface of the first wiring layer exposed from the surface of the first wiring layer is smaller than the roughness of the second exposed surface of the second wiring layer exposed from the surface of the insulating layer on the external connection surface side. . [Selection] Figure 1 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/TW-I736080-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2020188923-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-WO2020188923-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-7137292-B2 |
| priorityDate |
2015-10-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |