| abstract |
A semiconductor device that achieves miniaturization while maintaining good characteristics and a semiconductor device that achieves three-dimensional high integration while maintaining good characteristics of the semiconductor devices that achieve these miniaturization. A wiring 111 embedded in an insulating layer 130, an oxide semiconductor layer 144 over the insulating layer, a source electrode 142a and a drain electrode 142b electrically connected to the oxide semiconductor layer, and an oxide semiconductor layer And the gate insulating layer 146 provided between the gate electrode 148a, the oxide semiconductor layer, and the gate electrode. The insulating layer is formed so as to expose a part of the upper surface of the wiring, and the wiring is in a region where a part of the upper surface is higher than a part of the surface of the insulating layer and exposed from the insulating layer. And electrically connected to the source electrode or the drain electrode. A part of the surface of the insulating layer that is in contact with the oxide semiconductor layer has a root mean square roughness of 1 nm or less. [Selection] Figure 1 |