| abstract |
In the example described, integrated circuit (100) includes a semiconductor material (104). The first gate structure (108) includes a gate dielectric layer (112) and a gate (114). The second gate structure (118) includes a gate (122) that does not overlap the sidewall (142) of the field oxide (106). The SiGe source / drain region (138) has a top edge (140) that does not extend more than one third of the depth of the SiGe source / drain region (138) from the top surface of the semiconductor material (104). Between the first and second gate structures (108, 118). Dielectric spacers (124, 152) extend over the SiGe source / drain regions (138) and are adjacent to the lateral surface of the gate (122). The first and second gate structures (108) are such that the contact (160) is in direct contact with the metal silicide (156) on the SiGe source / drain region (138) at least half of the bottom of the contact (160). , 118). |