| abstract |
A three-dimensional integrated circuit comprising a top layer nanowire transistor formed on the bottom layer of a CMOS transistor having inter-layer vias, intra-layer vias, and metal layers for connecting various CMOS and nanowire transistors to each other. The top layer initially starts as a lightly doped region on the first wafer, over which an oxide layer is formed. Hydrogen ion implantation forms a cleavage interface. The first wafer is flipped over and oxidatively bonded to a second wafer with CMOS devices, and the cleavage interface is thermally activated so that a portion of the lightly doped region remains bonded to the bottom layer. It becomes. Nanowire transistors are formed in the top layer. The source and drain for the top layer nanowire transistor are formed by in-situ doping during epitaxial growth. After the oxidative bonding, the remaining process steps are performed at a low temperature so as not to damage the metal interconnect. |