http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2016181619-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f4a8faea375370b67c9d71e67db32bcd |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-46 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-40 |
| filingDate | 2015-03-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_353c58199973cb589ffed43f34378688 |
| publicationDate | 2016-10-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2016181619-A |
| titleOfInvention | Wiring board manufacturing method |
| abstract | A method of manufacturing a wiring board having high electrical insulation reliability between via conductors is provided. A first region that is narrower than the galvano area E and has a large number of via holes V formed at a high density, and a second region that is wider than the galvano areas A to D and has a large number of via holes V formed at a low density. A method of manufacturing a wiring board 10 including a step of forming a large number of via holes V by laser processing the wiring board area 10P into a plurality of galvano areas A to E on an insulating sheet 1P having a wiring board area 10P including Then, the first region is laser processed by one galvano area E, and the second region is divided into a plurality of galvano regions A to D for laser processing. [Selection] Figure 3 |
| priorityDate | 2015-03-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 16.