| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fdf3b6ced3d7710ec0bc0addb67a1cc9 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C14-0063 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-412
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1255
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1214
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-1225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B99-00 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K19-096
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K3-356
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8244
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786 |
| filingDate |
2016-01-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_81723184b653bb14ea22e1939181e4ff
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7806e224463ccccbdbf7d9c175beee9b |
| publicationDate |
2016-07-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2016136725-A |
| titleOfInvention |
Semiconductor integrated circuit |
| abstract |
A semiconductor integrated circuit that reduces power consumption of a memory device, reduces the area of the memory device, and reduces the number of transistors included in the memory device. A comparator for comparing potentials of a first output signal and a second output signal, a first memory unit having a first oxide semiconductor transistor and a first silicon transistor, A second memory section 203 having a second oxide semiconductor transistor 102 and a second silicon transistor 116; and an output potential determiner 204 for determining the potential of the first output signal and the second output signal. Have. One of the source and the drain of the first oxide semiconductor transistor is electrically connected to the gate of the first silicon transistor, and one of the source and the drain of the second oxide semiconductor transistor is It is electrically connected to the gate of the second silicon transistor. [Selection] Figure 2 |
| priorityDate |
2011-05-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |