| abstract |
In a configuration for stopping and returning a power supply voltage, the number of signals for controlling a semiconductor memory device from an external circuit is reduced. A memory circuit including a transistor including an oxide semiconductor in a semiconductor layer, a capacitor element that accumulates charges for reading data held in the memory circuit, and a capacitor element that controls accumulation of charges in the capacitor element The charge storage circuit, the data detection circuit for controlling the data reading state, and the capacitor element by the charge storage circuit by the power supply voltage signal and the signal obtained by delaying the power supply voltage in the period immediately after the power supply voltage is supplied. And a timing control circuit that generates a signal for accumulating the electric charge and an inverter circuit that inverts and outputs the potential of one electrode of the capacitor. [Selection] Figure 1 |