| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b3310ea86f3c492f6c09d7be6592866d |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2203-0307
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2203-0392
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K2203-107
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y10T29-49165 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-46
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-002
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-0038
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H05K3-429 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C23C28-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C25D5-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C25D1-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C25D5-12
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/C25D1-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-46
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H05K3-00 |
| filingDate |
2014-05-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_874d41772d91fc09eda85aed53fb4447
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a6bea3c39a3aeef08800324b1f9fb17c |
| publicationDate |
2015-03-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2015046570-A |
| titleOfInvention |
Multilayer printed circuit board manufacturing method |
| abstract |
A method of manufacturing a multilayer printed circuit board capable of processing holes without causing deterioration of a resin and damage of an inner layer circuit is provided. A method of manufacturing a multilayer printed circuit board according to the present invention includes a step of preparing a substrate 100 in which an insulating layer 102 and a surface-treated copper foil 103 are sequentially formed on an inner layer circuit 101, and a surface-treated copper. A part of the foil 103 and the insulating layer 102 is primarily processed with a laser to form a hole exposing the insulating layer 102, and the exposed insulating layer 102 is secondarily processed with a chemical etching solution to form an inner layer circuit 101. A step of forming a conduction hole 201 that exposes the substrate. [Selection] Figure 6 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2017152484-A |
| priorityDate |
2013-08-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |