| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0950e9df7f0e1b73efee1bda859951ad |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-27
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5642
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-26 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-04
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10 |
| filingDate |
2012-09-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_08b64fd00d9a7011566e2c472445f2bc
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0e235bab01b663b8eb9047d09c7dd7ed
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7ccf14f0c3ed68953bee8062f5566ada |
| publicationDate |
2014-03-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2014049173-A |
| titleOfInvention |
Semiconductor memory device |
| abstract |
An object of the present invention is to more accurately realize a high-speed data bus. A semiconductor memory device includes a memory core having a memory cell array and a peripheral circuit that transfers data input to a pad section to the memory core. The peripheral circuit 12 includes a first region in which a first data bus having a first wiring resistance is disposed, and a second data bus having a second wiring resistance lower than the first wiring resistance. Second region. The first area transfers data in parallel at the first operating speed, and the second area transfers data serially at a second operating speed that is faster than the first operating speed. [Selection] Figure 4 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2022500856-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9093159-B2 |
| priorityDate |
2012-09-04-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |