http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2014049172-A

Outgoing Links

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filingDate 2012-09-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5b323fb35ffc6b225bf5ad969e6b430a
publicationDate 2014-03-17-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2014049172-A
titleOfInvention Semiconductor memory and memory system
abstract The power consumption of a semiconductor memory is reduced. A semiconductor memory according to the present embodiment includes a memory cell array including a plurality of memory cells, a memory core including first and second circuits for controlling operations of the memory cell array, and a memory core. An input / output circuit 20 that controls input / output of signals between the memory core 1 and the outside of the memory core 1, and first and second power supplies 81, 82, and three or more different drive voltages V 1, V 2, V And a power supply circuit 80 that applies SS to the memory core 10 and the input / output circuit 20. The first drive voltage V CC1 is applied to the first circuit, the second drive voltage V CCQ is applied to the input / output circuit 20, and the third drive voltage V CC2 is applied to the second circuit. [Selection] Figure 4
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-108304905-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-104881249-A
priorityDate 2012-09-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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Total number of triples: 21.