http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2014038882-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0950e9df7f0e1b73efee1bda859951ad |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-27 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-35 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-27 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-35 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247 |
| filingDate | 2012-08-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f9dfcac194946a3781550777e175bf0c |
| publicationDate | 2014-02-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2014038882-A |
| titleOfInvention | Semiconductor memory device |
| abstract | A semiconductor memory device capable of being miniaturized and having a high withstand voltage is provided. A memory unit is provided in a semiconductor substrate and includes a string in which a plurality of memory cells for storing data are connected in series, and a bit line switch circuit. The bit line switch circuit is a word connected to the bit line and source line connected to both ends of the string and the control gate of the memory cell to write and read data to and from each memory cell of the storage unit. Connected to the line. Then, the bit line wiring that is connected to the bit line of the bit line switching circuit, the high-potential side wiring portion (first wiring part) consisting of the bit line wiring BL HV on the high potential side R HV and the low potential side of the bit line wiring A dummy wiring portion (third wiring) provided with a dummy line DM to which a potential is not applied is arranged in a low potential side wiring portion (second wiring portion) R LV made of BL LV via a dividing portion. Part) RD is disposed. [Selection] Figure 1 |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-9653167-B2 |
| priorityDate | 2012-08-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 29.