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filingDate 2011-06-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationDate 2013-08-22-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber JP-2013533624-A
titleOfInvention Punch-through suppression transistor
abstract An advanced transistor with a punch-through suppression configuration includes a gate having a length Lg, a well doped to have a first concentration of dopant, and a screen region located below the gate and having a second concentration of dopant. Including. The second concentration of dopant may be higher than 5 × 10 18 dopant atoms / cm 3 . At least one punch-through suppression region is disposed below the gate and between the screen region and the well. The punch-through suppression region has a third concentration of dopant between the first concentration and the second concentration. A bias voltage can be applied to the well region to adjust the threshold voltage of the transistor.
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