| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a04ec82c01a5765a0fb9c6c0d8a9abba
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_9a9aad45e5465bd5d3e7e503b2b16c65 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D10-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2209-483
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2209-5011 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-466
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-4893
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-38
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F1-3203
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-46
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-5038
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F15-80
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F9-5027 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F1-32
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F9-48 |
| filingDate |
2013-07-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_04dbcea2acbe74d816f05280ac302764 |
| publicationDate |
2013-11-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2013239199-A |
| titleOfInvention |
Scheduling in multi-core architecture |
| abstract |
An executable transaction is scheduled in a multi-core processor having a plurality of processor elements. At least one processor element in a multi-core processor includes reconfigurable logic that is reconfigurable at runtime, listing executable transactions in an executable state for each configuration of the reconfigurable logic; Providing a configuration queue of executable transactions allocated to individual configurations of reconfigurable processor elements, and reconfiguring the content of the configuration queue associated with the currently selected configuration instance for execution Outputting to a valid processor element and switching the currently selected configuration instance when a predefined threshold is reached. [Selection] Figure 39 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-7075888-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10459773-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2017199383-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2019528490-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-WO2017199383-A1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-11120036-B2 |
| priorityDate |
2005-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |