| abstract |
A semiconductor memory device with high-speed operation and low power consumption is provided. Furthermore, a semiconductor storage device is provided in which the storage capacity per unit area is increased and the capacity of the capacitor is increased. A memory cell CL includes two or more sub memory cells SCL each including a word line WL, a bit line BL, a first capacitor Cb, a second capacitor Cf, and a transistor Tr. The memory cells SCL are stacked, and the transistor is provided with a first gate and a second gate through a semiconductor film, and the first gate and the second gate are connected to the word line WL, and the transistor One of the source and the drain is connected to the bit line BL, the other of the source and the drain of the transistor is connected to the first capacitor Cb and the second capacitor Cf, and the first gate and the second gate of the transistor in each of the sub memory cells SCL. This is a semiconductor memory device in which two gates overlap and are connected. [Selection] Figure 1 |