| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8244
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-49
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-423
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-417
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-41
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate |
2011-11-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3bca60e11ea5cabf6bf9d4c65da0e3a6
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_62bda92ebb6b753395cadcd2de2ad402 |
| publicationDate |
2013-05-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2013105852-A |
| titleOfInvention |
Semiconductor device and manufacturing method of semiconductor device |
| abstract |
An on-characteristic of a miniaturized transistor is improved. Miniaturized transistors are manufactured with high yield. An oxide semiconductor layer including a pair of low-resistance regions and a channel formation region sandwiched between the low-resistance regions, a first gate electrode layer overlapping with the channel formation region with a gate insulating layer interposed therebetween, A pair of second gate electrode layers that are in contact with the side surface in the channel length direction of the gate electrode layer and the upper surface of the gate insulating layer and overlap with the pair of low resistance regions, and side end portions on the second gate electrode layer A semiconductor device including a pair of side wall insulating layers overlapping with a side end portion of a second gate electrode layer is provided. [Selection] Figure 1 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2016027649-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2019050400-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2020188643-A1 |
| priorityDate |
2011-11-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |