| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0950e9df7f0e1b73efee1bda859951ad |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2029-0411
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-1044
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F2212-7208
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F12-0246 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-1048
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-1072
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-52
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F11-1666 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-16 |
| filingDate |
2011-09-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7b841400fd931b80ee328b70f02b14d0 |
| publicationDate |
2013-04-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2013069171-A |
| titleOfInvention |
Memory system and control method thereof |
| abstract |
PROBLEM TO BE SOLVED: To provide a memory system capable of writing data reliably and at high speed and a control method thereof. The memory system includes first and second districts (31a, 31b) and a control unit (21). The first and second districts 31 a and 31 b each have a memory cell array 32. The control unit 21 receives a write command and an address for simultaneously writing the first data to the first and second districts 31a and 31b, and simultaneously receives the first data to the first and second districts 31a and 31b. Write. [Selection] Figure 2 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2017045405-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10353852-B2 |
| priorityDate |
2011-09-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |