| abstract |
In a stacked LSI, low latency and high throughput communication is realized between LSIs. By adopting a connection topology in which one transmission circuit (TR_00T) and a plurality of reception circuits (TR_10R, TR_20R, TR_30R) are connected to one through electrode group (for example, TSVGL_0). Eliminates the need for mediation. In particular, in order to enable this connection topology even when a plurality of the same LSIs are stacked, in each stacked LSI, each through-electrode port is designated for transmission or reception, and each through-electrode Equipped with a rewritable memory element for specifying port address allocation. [Selection] Figure 1 |