| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_6b822ee046eb6c45d1e3bd9ce9c1782e |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-005
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-788
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-792 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C14-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C14-0054
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-34
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-40
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7869
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C14-0009 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K3-356
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-115
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8247
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-792
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-788
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-786
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K3-037 |
| filingDate |
2012-02-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a2f3e87a0de955b4120d898c3517094b |
| publicationDate |
2013-01-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
JP-2013009300-A |
| titleOfInvention |
Memory circuit |
| abstract |
An object of the present invention is to provide a memory circuit of a signal processing device that can suppress power consumption by stopping power supply for a short time and can be initialized without causing malfunction when power is resumed. A data signal stored in a volatile storage unit is held in a nonvolatile storage unit while power is not supplied to the storage circuit. In the nonvolatile memory portion, a data signal held in the capacitor is held for a long time by using a transistor with an extremely low off-state current. In this way, the nonvolatile storage unit maintains the logical state even while the supply of power is stopped. In addition, the data signal held by the capacitor when the power is stopped is set to a potential that does not cause a malfunction by bringing the reset circuit into a conductive state when the power is resumed. [Selection] Figure 1 |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2015195331-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-102125692-B1
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/KR-20140113478-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2014200077-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/US-10090023-B2
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2014207667-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2014209726-A |
| priorityDate |
2011-02-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |