| abstract |
A new logic-in-memory structure is provided. In addition, a signal processing circuit with lower power consumption is provided. In addition, an electronic device with lower power consumption is provided. A circuit in which a memory function and an arithmetic function are combined is provided by forming a memory element using a transistor with low off-state current. By using a transistor with low off-state current, charge can be held between one of a source and a drain of a transistor with low off-state current and the gate of another transistor. Therefore, a node or the like between one of a source and a drain of a transistor with low off-state current and the gate of another transistor can be used as a memory element. Further, the leakage current accompanying the operation of the adder can be remarkably reduced. Thereby, it is possible to construct a signal processing circuit with low power consumption. [Selection] Figure 1 |