http://rdf.ncbi.nlm.nih.gov/pubchem/patent/JP-2012252731-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f56b5174f7d196258707ccf1d609796e |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4097 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4091 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-14 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4094 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4094 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-401 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-407 |
| filingDate | 2011-05-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_67e14433a1ef1a313d692b07962a3772 |
| publicationDate | 2012-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | JP-2012252731-A |
| titleOfInvention | Semiconductor device |
| abstract | A hierarchical DRAM having a small circuit scale is provided. Each has a plurality of memory cells, a bit line connected to the memory cell, and a precharge circuit for precharging the bit line, and is arranged in a matrix in the row direction and the column direction. A plurality of sub-arrays, a column selection signal line extending along the column direction and selecting a column of the sub-array, and a main line for selecting a row of the sub-array extending along the row direction A word line and a precharge signal line for supplying a precharge signal to the precharge circuit, wherein at least two subarrays arranged side by side in the row direction or the column direction correspond to the precharge signal. Semiconductor devices controlled by the same logic. [Selection] Figure 2 |
| priorityDate | 2011-05-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 33.